The present invention generally relates to an integrated circuit having a bipolar-CMOS circuit, and particularly to a flip-flop circuit having a bipolar-CMOS circuit.
Currently, a flip-flop is widely used in various electronic circuits such as a register and a latch circuit. As is well known, a flip-flop is formed by NAND gates or NOR gates. Generally, a flip-flop made up of NAND gates operates faster than a flip-flop made up of NOR gates.
Referring to FIG. 1, there is shown a conventional flip-flop composed of NAND gates. NAND gates G1 and G2 are supplied with complementary inputs A and B, respectively. Complementary outputs Q and XQ of the NAND gates G1 and G2 are supplied, as inputs, with the NAND gates G2 and G1, respectively.
A NAND gate outputs a low logic level (hereinafter simply referred to as L) when both the inputs are a high logic level (hereinafter simply referred to as H). For example, when A=H and B=L, the flip-flop has a stable state where Q=L and XQ=H. In this state, when the inputs A and B change such that A=L and B=H, the two inputs of the NAND gate G1 are switched to L and H and the output Q thereof is changed from L to H. Thus, both the inputs of the NAND gate G2 change to H, and the output XQ thereof is switched from H to L. In this state, the flip-flop is settled.
It is noted that the output of one of the NAND gates does not change from H to L until the output of the other NAND gate has changed to H. For the above-mentioned example, the output of the NAND gate G2 changes from H to L when the output of the NAND gate G1 has changed to H. That is, there is a delay of time between the outputs Q and XQ. This delay is equal to one stage of NAND gate. The delay occurring between the outputs Q and XQ causes a skew.
The delay between the outputs Q and XQ is described in detail below with reference to FIG. 2, which is a circuit diagram of an example of the structure for the flip-flop shown in FIG.1. The NAND gate G1 includes P-channel metal oxide semiconductor transistors P21 and P22 connected to a high-potential power source V.sub.DD, and N-channel metal oxide semiconductor transistors N21 and N22. Hereinafter, a P-channel metal oxide semiconductor is simply referred to as PMOS transistor, and an N-channel metal oxide semiconductor is simply referred to as NMOS transistor. The PMOS transistors P21 and P22, and the NMOS transistors N21 and N22 define a NAND logic. An NPN bipolar transistor Q21 is used for charging the output Q quickly, and an NPN bipolar transistor Q23 is used for discharging the output Q quickly. That is, the bipolar transistors Q21 and Q23 function to drive a load coupled to the output of the NAND gate G1. It can be seen from the above description that the NAND gate G1 is a bipolar-CMOS (Bi-CMOS) circuit. NMOS transistors N23 and N24 are used for drawing a charge at the base of the bipolar transistor Q21. An NMOS transistor N25 connected to a low-potential power source (ground for the illustrated example) functions to draw a charge at the base of the bipolar transistor Q23.
The NAND gate G2 is formed in the same manner as the NAND gate G1, and consists of PMOS transistors P23, P24, NMOS transistors N26-N30, and bipolar transistors Q22 and Q24.
It is now assumed that the flip-flop is being settled in the state where A=H, B=L, Q=L, and XQ=H. The ON/OFF state of each of the transistors in this state is illustrated in FIG. 2. When the inputs A and B change from H and L to L and H, respectively, the states of the transistors change as follows. The PMOS transistor P21 changes from OFF to ON, and the NMOS transistors N21 and N23 change from ON to OFF. Thereby, the bipolar transistor Q21 turns ON. A charge passes through the bipolar transistor Q21, and is supplied to the output Q of the NAND gate G1. Thus, the output Q is changed from L to H.
On the other hand, when the input B changes from L to H, the PMOS transistor P24 is switched from ON to OFF, and the bipolar transistor Q22 turns OFF. Further, the NMOS transistors N26 and N28 turn ON. The aforementioned change in the output Q from L to H is transferred to the gates of the NMOS transistors N27 and N29, so that the NMOS transistors N27 and N28 turn ON. A charge at the output XQ passes through the NMOS transistors N26 and N27. Then a part of the charge is applied to the base of the bipolar transistor Q24, and the remaining charge passes through the NMOS transistor N30. The bipolar transistor Q24 is turned ON by the application of part of the charge from the output XQ. Thereby, the charge at the output XQ is allowed to pass through the bipolar transistor Q24, so that the discharge of the output XQ is accelerated. Then the bipolar transistor Q24 turns OFF again when the output XQ is sufficiently discharged. A change in the output XQ from H to L is transferred to the gates of the NMOS transistors N22 and N24, so that they turn OFF. As a result, the flip-flop is settled in the state where Q=H and XQ=L.
It can be seen from the above-mentioned operation that the state of the NAND gate G2 does not change until the state (output) of the NAND gate G1 changes. Thus, the time difference in change between the outputs Q and XQ occurs